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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3 Device Configuration
www.ti.com
3.1
System Registers
The system registers in Table 3-1 configure the device and monitor its status.
Table 3-1. Idle Control, Status, and System Registers
CPU WORD
ADDRESS
0001h
0002h
1C00h
1C02h
1C03h
1C04h
1C05h
1C14h
1C16h
1C17h
1C18h
1C19h
1C1Ah
1C1Bh
1C1Ch
1C1Dh
1C26h
1C28h
1C2Ah
1C2Bh
1C2Ch
1C2Dh
1C30h
1C31h
1C32h
1C33h
1C36h
1C37h
1C38h
1C39h
1C3Ah
1C40h
ACRONYM
ICR
ISTR
EBSR
PCGCR1
PCGCR2
PSRCR
PRCR
TIAFR
ODSCR
PDINHIBR1
PDINHIBR2
PDINHIBR3
DMA0CESR1
DMA0CESR2
DMA1CESR1
DMA1CESR2
ECDR
RAMSLPMDCNTLR1
RAMSLPMDCNTLR2
RAMSLPMDCNTLR3
RAMSLPMDCNTLR4
RAMSLPMDCNTLR5
DMAIFR
DMAIER
USBSCR
ESCR
DMA2CESR1
DMA2CESR2
DMA3CESR1
DMA3CESR2
CLKSTOP
DIEIDR0 (1)
Register Description
Idle Control Register
Idle Status Register
External Bus Selection Register
Peripheral Clock Gating Control Register 1
Peripheral Clock Gating Control Register 2
Peripheral Software Reset Counter Register
Peripheral Reset Control Register
Timer Interrupt Aggregation Flag Register
Output Drive Strength Control Register
Pull-Down Inhibit Register 1
Pull-Down Inhibit Register 2
Pull-Down Inhibit Register 3
DMA0 Channel Event Source Register 1
DMA0 Channel Event Source Register 2
DMA1 Channel Event Source Register 1
DMA1 Channel Event Source Register 2
EMIF Clock Divider Register
DARAM Sleep Mode Control Register 1
SARAM Sleep Mode Control Register 2
SARAM Sleep Mode Control Register 3
SARAM Sleep Mode Control Register 4
SARAM Sleep Mode Control Register 5
DMA Interrupt Flag Aggregation Register
DMA Interrupt Enable Register
USB System Control Register
EMIF System Control Register
DMA2 Channel Event Source Register 1
DMA2 Channel Event Source Register 2
DMA3 Channel Event Source Register 1
DMA3 Channel Event Source Register 2
Peripheral Clock Stop Request/Acknowledge Register
Die ID Register 0
COMMENTS
see Section 3.6.1 .
1C41h
DIEIDR1
(1)
Die ID Register 1
1C42h
1C43h
DIEIDR2 (1)
DIEIDR3 (1)
Die ID Register 2
Die ID Register 3
1C44h
DIEIDR4
(1)
Die ID Register 4
1C45h
1C46h
1C47h
DIEIDR5 (1)
DIEIDR6 (1)
DIEIDR7 (1)
Die ID Register 5
Die ID Register 6
Die ID Register 7
7004h
LDOCNTL
LDO Control Register
see Figure 3-1 .
(1)
This register is reserved.
48
Device Configuration
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